Oct 16
Top Secret/SCI
Mid Level Career (5+ yrs experience)
Occasional travel
Engineering - Electrical
Arlington, VA (On-Site/Office)
FPGA Verification Engineer to join our classified hardware development team in Arlington, VA (TS//SCI clearance required). The ideal candidate will develop and implement comprehensive verification strategies, including formal methods, for complex FPGA designs in high-assurance applications.
You will develop UVM-based verification environments, create and execute formal verification test plans, implement formal property verification and equivalence checking, and develop coverage-driven verification methodologies.
Key responsibilities include creating automated test frameworks, applying formal methods for security-critical design blocks, and collaborating with RTL developers to ensure design quality. Requirements include a Bachelor's degree in Electrical/Computer Engineering.
7+ years of FPGA verification experience, expert knowledge of SystemVerilog and UVM, and demonstrated experience with formal verification tools and assertion-based verification.
Desired skills include experience with Cadence JasperGold or similar formal tools, knowledge of security protocols and formal security proofs, SystemVerilog Assertions (SVA), and background in mathematical logic and proof systems.
Current TS/SCI clearance is required.
You will develop UVM-based verification environments, create and execute formal verification test plans, implement formal property verification and equivalence checking, and develop coverage-driven verification methodologies.
Key responsibilities include creating automated test frameworks, applying formal methods for security-critical design blocks, and collaborating with RTL developers to ensure design quality. Requirements include a Bachelor's degree in Electrical/Computer Engineering.
7+ years of FPGA verification experience, expert knowledge of SystemVerilog and UVM, and demonstrated experience with formal verification tools and assertion-based verification.
Desired skills include experience with Cadence JasperGold or similar formal tools, knowledge of security protocols and formal security proofs, SystemVerilog Assertions (SVA), and background in mathematical logic and proof systems.
Current TS/SCI clearance is required.
group id: 91164107